The hardware implementation of deep neural networks (DNNs) has recentlyreceived tremendous attention: many applications in fact require high-speedoperations that suit a hardware implementation. However, numerous elements andcomplex interconnections are usually required, leading to a large areaoccupation and copious power consumption. Stochastic computing has shownpromising results for low-power area-efficient hardware implementations, eventhough existing stochastic algorithms require long streams that cause longlatencies. In this paper, we propose an integer form of stochastic computationand introduce some elementary circuits. We then propose an efficientimplementation of a DNN based on integral stochastic computing. The proposedarchitecture has been implemented on a Virtex7 FPGA, resulting in 45% and 62%average reductions in area and latency compared to the best reportedarchitecture in literature. We also synthesize the circuits in a 65 nm CMOStechnology and we show that the proposed integral stochastic architectureresults in up to 21% reduction in energy consumption compared to the binaryradix implementation at the same misclassification rate. Due to fault-tolerantnature of stochastic architectures, we also consider a quasi-synchronousimplementation which yields 33% reduction in energy consumption w.r.t. thebinary radix implementation without any compromise on performance.
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